Correct Designs Course Syllabus
Title: Advanced Verification Planning
Description: This course provides the student with knowledge to develop a true coverage-driven verification plan. Language and methodology classes only describe how to write/code a testbench (i.e. a verification environment), but this course explains how to write an effective, high-quality verification plan. No one builds a bridge without a blueprint, and engineers should not build a testbench without a first having written an effective test plan. The resulting verification environment will be effective only if comprehensive testbench requirements, based on design features/requirements, are captured in the verification plan.
Not only does this class teach the student how to write a test plan, but the student will understand how to create an “executable” plan that enables automation during the verification process, to track progress against the test plan. Novel technology is utilized to allow the verification engineer to “map” features in a functional specification document to verification goals (not just functional coverage, but also code coverage and checking requirements).
This unique class demonstrates how to exploit the Enterprise Planner functionality within Enterprise Planner.
Length: 2 days
Audience: Verification Engineers
Prerequisites: Knowledge/experience verifying RTL logic designs. It is beneficial, but not required, for students have a working knowledge of the Enterprise Manager
Software Requirements: Cadence Enterprise Manager
Related Courses: e Language Basic Training, e Language Developer Training
Learning Objectives:
The student is able to correctly use the verification planning methodology in his project. He is able to use the Enterprise Planner technology to develop verification plans with and without the annotation technology. He demonstrates these skills by developing a verification plan for the XDMAC.
Agenda:
Day 1
- Develop Verification Plan and Coverage and Check Models
- Verification Planning Automation
- Measuring Verification Progress
- Using a Feature Based Verfication Plan
- Enabling the Verification Plan as Tracking Metric
- Identifying DUT Features
- Example XDMAC DUT Features
- Structure a Verification Plan in EP
- (LAB) Brainstorm the XDMAC Verfication Plan
- Identify Coverage and Check Metrics
- (LAB) Create Coverage and Check Entities for a Verification Plan
- Integrate the Plan in a vM based Flow
- (LAB) Create and Use a vM Compliant Plan
- Annotate Specification Documents to Plans and Manage Spec Changes
- Specification based Development
Day 2
- Annotate Documents to a Verification Plan
- (LAB) Annotate the XDMAC Functional Specification
- Work with Annotator Results in the Planner
- Detect Changes between Annotated Plan Elements and Documents
- (LAB) Include Annotator Information, Synchronize Plan to Document Changes
- Demonstrate e-code generation functionality
- Reuse Plans and Configure Plans and Coverage Entities
- Reuse existing Verification Plans in Project
- (LAB) Integrate the DMA Plan into the XDMAC Plan
- Configure Plan Structure and Coverage Metrics
- (LAB) Create the XDMAC Project Plan
- (LAB) Export the Functional Coverage Model as an e Implementation