Correct Designs Course Syllabus

Title: SystemVerilog Assertions In-depth

Description: This SystemVerilog course provides the student with an in-depth introduction to learning and applying the most useful constructs and concepts provided by the SystemVerilog Assertion constructs. The course demonstrates the benefits of using SystemVerilog Assertions, and how to make designs more efficient and effective using SVA constructs. 

This class includes an extensive amount of material in 2 days of training.  At the end of the course, students will have the ability to apply any of the SVA constructs to meet their real world application requirements. The course contains a number of labs that reinforce learning the full set of SVA constructs and complex assertion based verification techniques used in modern design flows.  Students will have the opportunity to take home all of the material for use as a reference.

Length: 2 days       

Audience: Design and Verification Engineers

Prerequisites: Knowledge/experience in designing and simulating RTL logic designs. It is beneficial, but not required, for students have a working knowledge of the Verilog hardware description language.

Software Requirements: Synopsys VCS, Mentor QuestaSim, or Cadence IUS

Related Courses: SystemVerilog Fundamentals with an SVA overview, Verification Using SystemVerilog, SystemVerilog for RTL Designers

Learning Objectives:

In this course the student will be able to:

• Take advantage of Assertion-Based Verification (ABV) techniques on real designs using SystemVerilog Assertions (SVA) constructs.
• Examine, in detail, the structure of SystemVerilog Assertions and demonstrate the full range of language features to specify checking, coverage and stimulus constraints on the most complex designs using efficient, pragmatic assertion writing techniques.
• Describe the SystemVerilog Assertions language constructs and how they are used to verify design intent in simulation, emulation and formal environments.
• Apply advanced function coverage techniques to real designs taking advantage of complex SystemVerilog assertion constructs and vendor tool features designed for coverage.
• Take advantage of the pre-existing Open Verification Library (OVL) assertion library when applicable and understand the benefits and techniques for writing reusable assertion libraries.

Agenda:

Day 1

• Introduction to SystemVerilog Assertions
• What is an assertion
• Assume Guarantee Principles and Assertion Reuse
• Assertion layers
• Types of Assertions
• Concurrent Assertions
• Timing and signal sampling
• Action blocks
• Terminating Evaluations
• Context and Scope
• Instancing options
• Basis System Functions
• Implication Operators
• Sequences
• Property with a Sequence
• Sequence Concatenation
• Cycle Delay
• Time Delay Windows
• Beginning Delays
• Consecutive Repetition
• Consecutive Repetition Range
• Unbounded Consecutive Repetition
• Nonconsecutive Repetition
• Nonconsecutive Repetition Range
• Goto
• Advanced Sequences
• Advanced matching operators…
• First Match
• Throughout
• within
• OR Sequences
• AND Sequences
• Intersect Sequences (special AND)
• not Property Operator
• .ended Uses
• .matched Method
• Saving and printing data
• Calling Routines from Sequences
• Local Variables
• SVA Scoreboard
• Reuse
• Formal Arguments to Sequences
• Formal Arguments to Properties
• Clocking Options
• Simple coverage examples

Day 2

• System Functions
• $countones
• $countones
• $onehot0
• $onehot
• $isunknown
• $rose
• $fell
• $stable
• $past
• $sampled
• Concurrent assertions in procedural code
• Coverage
• Checker Coverage
• User Defined Coverage Goals
• Recommended Practices
• Open Verification Library (OVL)
• Clocks
• Reset
• X Checking
• Parameters
• Checkers
• Compile Options
• Functional Coverage Reporting
• Vendor Specific Assertion Libraries
• Assertion Control and Simulation Tools
• Generate blocks
• Procedural Controls
• Synopsys VCS
• Cadence IUS
• Mentor Questa