Correct Designs Course Syllabus
Title: e Language Developer Training
Length: 3 days
Audience: Verification Engineers
Prerequisites: e Language Basic Training. Knowledge/experience in simulating RTL logic designs.
Software Requirements: Cadence IES (Specman Elite)
Related Courses: e Language Basic Training
Description: This course teaches how to create a modular,
reusable verification environment using the e language and the Incisive®
Enterprise Specman Elite® tool. The course is based on a coverage driven
verification methodology which is applicable for a broad range of designs and
goes far beyond the traditional directed-test methodology. Lessons include
stimulus generation, checking results using scoreboards and assertions,
collecting and analyzing functional coverage and designing for reuse. The
material addresses verification methodologies for a broad range of designs. This
course provides hands-on experience, with a mix of lecture and labs.
Learning Objectives:
Upon completion of this course you will have a better understanding of verification methodologies, and be able to apply these methodologies to rapidly create an efficient environment for thorough design verification.
This course addresses:
· The design verification process
· Concepts and dynamic structures
· Automating constraint-driven random stimulus generation and variation
· Interfacing to the HDL design (driving and sampling)
· Constructing flexible and powerful stimulus sequences
· Implementing data and protocol/assertion checks
· Functional coverage
· Designing verification environments for reuse
· Debugging verification environments
Agenda:
Day 1
§ Architecting the Verification Environment
This section details the eRM architectural guidelines necessary to create reusable verification environments. To this end, this section also reviews in detail additional topics.
o ERM Environment architecture
o Checking architecture
o Stimulus architecture
o Partitioning of checking and stimulus
o BFMs, Monitors, Agents, sequence drivers, checker architecture, synchronizers and signal maps, envs.
o Like inheritance
o Units
o Inter-unit communication via reference
o Inter-unit communication via method_ports
o Port binding
o Elaborate phase
o Connect_pointers(), connect_ports() and check_generation() methods
o ERM file organization (eRM compliant directory structure)
o Benefits of eRM directory structure
o EDocs
o Protected, package & private
o Modules and more about imports
o Cyclic import issues
o Resolution of type names (namespaces in the e language)
o ERM legend and eRM diagrams
o Lab 7
§ Lunch
§ BFMs and Monitors
o Details of implementing simple_ports
o Using units to facilitate reuse (hdl_path())
o Port references
o Details of signal maps and synchronizers
o Pack/unpack
o Lab 8
Day 2
§ The Sequence Environment
Unlike the earlier section on sequences, this section details the steps the environment developer will need to make to create a sequences ready verification environment. Developing sequences and additional advanced sequences topics are also covered.
o Predefined sequence constructs
o The sequence statement and associated automatically generated code
o Architecture of a sequence enabled agent
o Connecting sequence drive to BFM
o Pull mode, try and get_next_item(), item_done etc …
o Sequences as method primitives
o Interrupt sequences
o Pre-run sequence execution
o Debugging sequences
o Lab 9 – Creating a sequence capable environment
§ Lunch
§ Verification Environment API
This section illustrates techniques to support proper testcase architecture.
o Topology variations & topology constraints
o Family testcase files
o Default subranges (contrasting soft constraints and constraint grouping)
o Non-contiguous ranges
o Abstracted range identifiers (control fields)
o Coordinated ranges for two or more fields
o Ranges influenced by environment topology
o Constraint grouping
o Lab 10 –Control knobs and sequences (done as a group)
§ Data Checking
o Data checking fundamentals and methodology
o The checking problem: Design intent, Specifications and planning
o Checking architecture and reuse
o Different types of checking (temporal vs. data)
o On-the-fly vs. post-run
o Reference models and degrees of accuracy
o Scoreboards
o Copy, deep_copy, deep_compare
o Relationships to the monitor
o Method ports
o Dut error reporting and associated actions
o Check effects
o Lab 11 – Data checking
Day 3
§ Temporal Checking
o The Expect statement
o Review basic temporal expressions and temporal operators
o Advanced temporal expressions and operators including the yield operator
o Debugging temporal expressions
o Lab 12 - temporal expressions
§ Advanced Coverage
o Hierarchical coverage models implemented with subtypes
o Per_instance, no_collect and weight coverage options
o Coverage grading and the effects on the coverage report
o Additional techniques for setting at_least threshold
o Per instance vs per type coverage
o Bucket set naming
o Removing coverage buckets
o Ranges
o Event coverage techniques
o Sequence coverage techniques
o Latency
o Checker coverage
o Reuse and extension of coverage groups, options and items
o Common pitfalls
o Lab 13 – Advanced Coverage
§ Lunch
§ Controlling the Verification Environment
This section covers three eRM topics: Modeling DUT reset in a Specman environment; coordinating the end of simulation; displaying activity messages
o Quit() method
o Rerun() method
o Methodology associated with properly resetting a verification environment with the DUT is driven through reset.
o The eRM objection mechanism
o The test done objection mechanism
o Methodology behind the objection mechanism
o Debugging the objection mechanism
o Message and messagef actions
o Message tags and verbosity
o Message loggers
o Message filtering
o Set Message
o Message output format
o Show message
o Lab 14 – Controlling the verification environment