Correct Designs Course Syllabus

Title: SystemC Modeling with SCV and TLM

Description: This course provides the student with an in-depth introduction to all of the features of SystemC including its application specific libraries, the SystemC Verification (SCV) and Transaction Level Modeling (TLM) libraries. SystemC requires a knowledge of many advanced C++ features so it first provides an overview of key C++ and object oriented programming (OOP) concepts that are used heavily by SystemC. It then covers the core SystemC library and fundamental SystemC concepts. Finally it shows how SystemC can be applied to modeling and verification using the TLM and SCV libraries. The class is a balanced mix of lecture and practical exercises. The exercises are targeted to be useful in real world applications. Students will have the opportunity to take home all of the material for use as a reference.

 

This class is an advanced programming class and does not focus on introductory software development topics. It is also not an object oriented programming (OOP) class although it makes heavy use of OOP principles. Due to the broad audience, the programming aspects of the class may be straightforward to students with a software development background but quite challenging to many with a logic design or architecture background. The initial C++ portion of the class is required in order to ensure the effectiveness of the SystemC specific training. If the students are already proficient in C++ then pacing can be tailored so that the C++ topics are used as a refresher.

 

Length: 5 days       

Audience: Software developers, architects, design and verification engineers

Prerequisites: Knowledge of C or C++ and structured programming. Proficiency with a text editor such as emacs or vi. Some experience with design modeling such as RTL design or high level modeling.

Software Requirements: None. Class can be taught using the open source OSCI SystemC simulator or with Synopsys VCS, Mentor QuestaSim, or Cadence IUS (ncsim).

Related Courses: Verification Using SystemVerilog, SystemVerilog for RTL Designers

Learning Objectives:

In this course the student will:

• Learn or review C++ language and standard library features that are used by SystemC including default function arguments, function overloading, namespaces, input/output streams, the standard template library, classes, automatic type conversions, operator overloading, polymorphism, run time type identification, inline functions, memory allocation, templates, and avoiding dangerous language constructs.
•  Learn the core SystemC library features such as modules, processes, interfaces, channels, ports, export, time, events, clocks, reporting.
• Learn the core SystemC data types.
• Learn the SystemC simulation scheduler.
• Learn how to use the Transaction Level Modeling (TLM) 2.0 library to create abstract models.
• Learn to use the SystemC Verification library to create constrained random stimulus for the model.

Agenda:

Day 1, 2

• C++, OOP overview

Day 3

• SystemC Core

Day 4

• TLM 2.0

 

Day 5

• SCV

 

 

Outline:

 

l       C++

�      Functions

■        Pass by value/reference

■        Default arguments

■        Exceptions

�      Variables

■        Built in data types

■        const

■        void

■        Deprecated C constructs

�      Streams

■        Standard library

■        Namespaces

�      User defined data types

■        public, protected, private

■        Special member functions

■        Automatic type conversions

■        this pointer

■        Operator overloading

■        Function overloading: ostream& operator <<

■        static and const members and methods

■        OOO design principles

■        Inline functions

�      STL

■        String, vector, list, set, map, ostringstream

■        Iterators

■        Algorithms

�      Variable scoping and memory allocation

■        Constants and literals

■        Stack, heap, globals

■        Scoping operator

■        Dynamic allocation

l       new/delete

l       new[]/delete[]

�      Inheritance

■        Function overloading

■        operator overloading

■        Polymorphism via virtual methods

■        Multiple inheritance

■        Virtual multiple inheritance

■        Pure virtual base classes

■        Interfaces

■        Run time type identification

■        Type casting: static_cast, dynamic_cast

�      Templates

■        Templated functions

■        Templated classes

l       SystemC

�      Basics

■        Namespaces

■        Modules

■        sc_time

■        clocks

■        events

■        Processes

l       sc_method

l       sc_thread

l       sensitivity lists

l       dynamic sensitivity

■        sc_main

■        Module instantiation

■        Verilog on top

■        SystemC on top

�      Reporting and debug

■        sc_report

■        sc_timestamp

■        gdb, Eclipse CDT, ddd, etc.

�      SC Data types

■        sc_int<>, sc_uint, sc_bigint<>, sc_biguint<>

■        sc_bv, sc_logic, sc_lv

�      Scheduler

■        Events

■        Time

■        Scheduler

�      Communication

■        Interfaces

l       Blocking versus non-blocking methods

■        Channels

■        Primitive channels

■        Included channels

l       sc_signal, sc_buffer, sc_signal_resolved, sc_fifo

l       Required methods to use in included channels

■        Deferred binding

l       Port, exports

l       Port binding policies

l       Event finders

l       register_port

�      TLM Interfaces

�      TLM Channels

�      Constrained random stimulus generation using SCV

�      Extras, as needed or requested, time allowing

■        Dynamic processes

■        sc_trace

■        refinement

■        adapters

■        register_port

■        default_event

■        writing event finders

■        writing primitive channels