Kevin Schott, Cofounder and Executive VP
Kevin has over 25 years of experience in logic verification of high-performance processor designs and simulation methodology development, including several years of management. In addition to being Vice President of Correct Designs, most recently Kevin has provided expert instruction, teaching SystemVerilog to verification and design engineers all over North America. He has developed the core training materials for a 1-week course in the SystemVerilog design and verification language.

In parallel Kevin taught the e language and e Reuse Methodology to hundreds of engineers worldwide as a certified Specman instructor. He developed all the training material for the Specman Elite 5-day class being used worldwide by a major EDA vendor.

After leading 3 years of product development for Severity1 (another company that Kevin co-founded in 2003), he sold software licenses for that product to Fortune 100 semiconductor companies. This software technology enabled verification engineers to automate the verification planning process. This technology was acquired by a major EDA vendor in 2006, through which Kevin led product enhancements, and supported its transfer to the new company.

In 2003, as part of the IBM, Toshiba, Sony partnership team developing "Cell" (a high-performance gaming processor used by Sony and others), he led a verification team to define and execute a system verification plan to simulate the Cell processor with 2 complex I/O chips. While personally writing thousands of lines of e code as a hands-on technical contributor, he led an international multi-site, multi-company development team (who were new to Specman) to execute a detailed test plan.

In 2000, while consulting at Agere, he wrote thousands of lines of e code as the simulation lead on a 10Gbit network processor classifier chip using self-checking, directed-random simulation methodology. He's developed test plans, correctness models, test cases, and perl code to produce a high quality simulation environment being used by dozens of his client's design and verification engineers.


BACKGROUND

After receiving a BSEE in 1983 from Tulane University in New Orleans, Kevin joined IBM and helped bring into production, a research-prototype simulation accelerator in Boca Raton, FL. In 1984, he supported the IBM DSL/1 logic design language, simulator, and synthesis tools. In 1986 he was technical lead on developing an 8-port communications adapter for the 9370 systems. Kevin was asked to manage a department of engineers developing PS/2 memory and communications adapters in 1988. After moving to Austin in 1990, Kevin staffed and managed large verification departments including the team working on the Power2 RISC chipset used in IBM workstations. He was asked to lead the verification of the 615 processor on assignment in Burlington, VT for one year in 1995. Upon his return to Austin, he led the verification teams for the 630 Power3 design, and the GigaProcessor Power4, the most complex processor developed by IBM. In 2000 before leaving IBM, he was one of only 3 verification engineers ever to reach the level of Senior Technical Staff Member in the company at that time.

 
©2009 Correct Designs, Inc. All rights reserved.