Recently, Steve has led, and assisted with, the development of a new set of comprehensive hardware design, verification and modeling courses offered by Correct Designs. He has also assisted clients with the development, deployment, training and support of Vera and SystemVerilog base class libraries for use world-wide. Steve has taught hundreds of students around the world how to use advanced verification methodologies and base class libraries using professional quality, multi-day courses developed by Correct Designs. Steve also has extensive experience developing reusable verification intellectual property (VIP) and VIP reuse standards.

Prior to his recent work at Correct Designs, Steve was the co-founder and president of Severity1 Incorporated, an EDA company specializing in advanced Verification planning software. Severity1 software was used my multiple Fortune 100 semiconductor companies for developing reusable, coverage driven verification plans. Severity1 was sold to a large EDA company in 2006. Steve oversaw business operations and was very involved with the product requirements, development, sales, marketing, training and product deployment.

Prior to Correct Designs and Severity1, Steve was a senior partner and project leader at Silicon Resources, an Austin based consulting and software company. Steve also managed a large verification team at IBM and provided technical leadership on the design and verification of POWERPC, x86 and System390 CPUs.

Steve received his Bachelor of Science degree from the Institute of Technology at the University of Minnesota.