Correct Designs consults with semiconductor companies on ways to improve verification methodologies reducing time to market and insuring product quality. The company also provides contracted resources to develop and implement the verification plan for complex digital logic chip designs.

Through consulting and contracting services, Correct Designs, Inc. integrates leading edge simulation methodologies with EDA and client point tools to enable overall verification solutions while increasing engineering productivity.

Correct Designs is a preferred N. American training partner for the premier technical training company, Doulos (http://www.doulos.com), for SystemVerilog and SystemC classes.

Correct Designs is a member of the:

• Synopsys SystemVerilog Catalyst program (Catalyst)
• Mentor Graphics Questa Vanguard program (Vanguard)
• Cadence Verification Alliance program (Alliance) . In addition Correct Designs is certified as a member of the Cadence Incisive Plan-to-Closure Methodology Qualified program, and has demonstrated expertise in IPCM verification planning & management as well as Universal Reuse Methodology. See Cadence links: IPCM Members List and IPCM Press Release