SystemVerilog Class (with UVM Intro)

This course provides the student with practical instruction for learning and applying the most useful constructs and concepts provided by the SystemVerilog language, SVA and UVM for verification. The course demonstrates the benefits of the language and library...

Specman Elite Advanced Training

This course provides the student with of advanced topics writing e code and using Specman Elite. Please contact Correct Designs for more details about this class. Days in Course Length Audience Verification Engineers Prerequisites Knowledge/experience verifying RTL...

e Language Developer Training

This course teaches how to create a modular, reusable verification environment using the e language and the Incisive® Enterprise Specman Elite® tool. The course is based on a coverage driven verification methodology which is applicable for a broad range of designs and...

e Language Basic Training

In this course you will learn how to effectively use a verification environment created with the e language for the Cadence Incisive® Enterprise Specman Elite® product (or the Cadence Incisive Unified Simulator, “IUS”). The course is based on a coverage driven...

Advanced Verification Planning

This course provides the student with knowledge to develop a true coverage-driven verification plan.  Language and methodology classes only describe how to write/code a testbench (i.e. a verification environment), but this course explains how to write an effective,...

Contact Us

For more information, please contact us with the form provided, or feel free to call us at the number below.

(512) 331-6393

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