In this course you will learn how to effectively use a verification environment created with the e language for the Cadence Incisive® Enterprise Specman Elite® product (or the Cadence Incisive Unified Simulator, “IUS”). The course is based on a coverage driven verification methodology which is applicable for a broad range of designs. The material only focuses on how to use an e-based Specman verification environment where it is assumed that someone else has actually developed the environment.
Days in Course Length
Audience
Verification Engineers
Prerequisites
- Knowledge/experience in simulating RTL logic designs
- It is beneficial, but not required, for students have a working knowledge of an object-oriented programming language.
Software Requirements
- Cadence IES (Specman Elite)
Learning Objectives
In this course, you will learn about:
- Coverage driven verification methodology
- e language basics
- Sequence stimulus generation
- Collection and analysis of functional coverage
This course provides hands-on experience, with a mix of lecture and labs.
After completing this course, you will have gained a better understanding of verification methodologies and be able to apply these methodologies while using an environment for thorough design verification.
The topics covered in this course include:
- The design verification process
- Object-oriented concepts and dynamic structures
- Automation of constraint-driven random stimulus generation and variation
- Constructing flexible and powerful stimulus sequences
- Functional coverage
- Debugging verification environments with realistic examples, the full range of language features.
Agenda
Introduction to Coverage Driven Methodology
This is an abstract chapter that describes coverage driven methodology and could be used to describe the methodology used in any coverage driven verification environment. Some of the topics include:
o Why we need a CDV methodology
o Coverage driven approach vs. directed approach
o Traditional stimulus vs. directed random stimulus
o The concept and necessity of constraints, coverage and stand alone checking
o Why is coverage so key in a directed random environment
o Verification planning, developing a coverage plan
o What are the key components of a CDV methodology, constraints, coverage & checking
o Where is functional coverage instrumented within the verification environment
- e Basics
This gives a quick overview of object oriented concepts and starts describing the basics of e syntax. Some of the topics include:
o Object oriented programming principles
o Basic e syntax
o Sized and unsized constants
o Enumerated types
o Importing e files
- Specman Basic Training DUT Spec
This short section reviews the Sample DUT used for the course.
- Lunch
- Lab 1 – Running Specman
- Stimulus Creation (and Labs 2 & 3)
Includes the following topics:
o Structs and fields
o Extending structs
o Specman memory foot print (i.e. how Specman manages memory)
o Generation and constraints (Implication, for each, weighted, soft etc …)
o Constraint resolution
o Implication constraints
o Basics on how the constraint solver works
o Generation order
o Pre-run vs. on the fly generation
o Methods
o Extending methods
o Procedural control elements of the e language (if, while, repeat, for loops)
o Lists and list methods
o Memory footprint of lists
o Conditional printing, message and messagef actions
o Basics on controlling message and messagef actions
o Lab 2 – Structs fields and Constraints
o Lab 3 – Generation methods and list
Day 1
- Coverage Driven Testbench Architectures
- Advanced Connections
- Clocking Block Introduction
- Using Clocking Blocks within Interfaces
- Virtual Interfaces
Day 2
Stimulus Variation
o Includes the following topics …
o Motivation for stimulus variations
o When inheritance
o Subtypes and control fields
o Applications of subtypes
o Extending enumerated types
o Additional reference topics
o Lab 4
- Interfacing to the simulator
o Test phases and test phase methods
o Accessing DUT signals via simple_ports and tic access
o Threads, TCMs
o Calling and starting TCMs
o Specman and simulator interaction (aka synchronizing with the simulator)
o Wait/sync actions contrasted
o Events:simulator events, automatic & explicit emission of events, sys.any
o Temporal language basics
o On events
o Debugging events: events chart, waving events etc …
- Lunch
- Using Sequences
This section explains the key role of eRM sequences. And teaching students how to write sequences, including modifying the main sequence to implement an entire testcase using eRM sequences. This section does not cover the specific details of how to make a verification environment eRM ready. These omitted details are covered in a later section.
o Basics of a BFM
o eRM Testbench architecture of an eRM sequences agent
o The need for eRM sequences (compare a non-eRM sequence driver with an eRM sequence driver).
o The sequence statement
o Sequences
o Sequence drivers
o The Main sequence
o The do action
o Sequence libraries
o Creating testcases with sequences
o Debugging sequences
o Scenario Builder
o Lab 5 – using sequences
- Introduction to Functional Coverage
This section acts as an introduction to coverage constructs in Specman. Additional advanced topics are covered in later sections.
o Functional coverage defined and related back to CDV methodology
o The specman coverage GUI
o From verification plan to coverage implementation
o Coverage groups
o Basic, Transition and cross coverage items
o Coverage group options
o Coverage items options including ranges
o Extending coverage groups
o Lab 6 – coverage
Related Courses
- e Language Developer Training