Recruiting

Correct Designs, Inc. is a rapidly growing company headquartered in Austin, Texas specializing in consulting and contracting services to a growing list of semiconductor companies. If you have experience in verification, RTL design, physical design or layout, and would like to take on a new challenging career, Correct Designs may be right for you.   Scroll down for specific Job Postings.

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We offer an opportunity to grow your skills in the latest design and verification technologies, the chance to work with senior-level industry professionals on exciting products, and of course great pay, and benefits. Correct Designs is looking for experienced semiconductor professionals.  If you have experience in verification, RTL design, physical design or layout, and would like to take on a new challenging career, Correct Designs may be right for you.

Required Experience

  • At least five years of applicable semiconductor experience.
  • A BSEE, BSCSE, BSCS or higher degree.

Desired Experience

  • SystemVerilog/UVM
  • VHDL
  • Verilog
  • FPGA design
  • Physical/Circuit Design
  • Layout

Our job openings vary considerably based on our current client needs so please feel free to submit your resume below if you have any of the desired skills listed above.

Contact Kathy Stokes for details regarding specific job openings after submitting a resume.  kathys@correctdesigns.com 

Specific Job Openings

Senior DV Engineers

Using state-of-the-art testbench architecture and tools, you will be responsible to assist in the design, implementation, and execution of verification plans for an ARM based SOC.  If you have experience in digital logic simulation and would like to take on a new challenging career, Correct Designs may be right for you.

Desired Experience:

  • At least five years of hardware RTL verification or design experience.
  • A BSEE, BSCSE, BSCS or higher degree.
  • Industry verification experience with one or more of the following:
  • SystemVerilog, UVM, ARM and SOC verification.  
Senior Verification Engineer

Using state-of-the-art testbench architecture and tools, you will be responsible to assist in the design, implementation, and execution of verification plans for various types of chip designs. If you have experience in digital logic simulation and would like to take on a
new challenging career, Correct Designs may be right for you.

Desired Experience:

  • At least five years of hardware RTL verification or design experience.
  • A BSEE, BSCSE, BSCS or higher degree.
  • Industry verification experience with one or more of the following:
  • SystemVerilog, UVM and/or Specman/e language
Senior Formal Verification Engineer
Formal verification of the next generation of microprocessors,
interconnect fabrics and memory controllers
- Write formal properties, constraints, assertions and covers, to
verify the architecture and microarchitecture of next
generation proprietary designs.
- Create new formal verification methodologies to enable widespread
adoption of formal verification within the design and verification
teams.
- Define metrics to quantify the progress of the formal verification
effort and processes to generate the metrics.
- Write RTL helper code to enable the most efficient reuse of vendor
provided formal verification IP.
- Job Requirement:
   - Deep experience in formal verification.
   - Significant experience writing formal properties: constraints,
assertions and covers.
   - Experience writing guided proofs.
   - Knowledge of general microprocessor architecture.
   - Knowledge of interconnect architecture.
   - Knowledge of general design and verification flow.
Education: BSEE required, MSEE preferred.

    Senior System Verilog Verification Engineer

    Experience Required:

    Strong SystemVerilog, plus UVM, VMM, OVM experience.

    Experience with driver, monitor, scoreboard development and stimulus development.

    Strong debug, regression triage.

    CPU Memory Subsystem, ARM experience a plus.

    Experience using system Verilog for coding drivers/monitors/scoreboards, UVM  a plus.

    Education: BSEE required, MSEE preferred. 

    Senior Test Engineer - San Jose

    Experience:

    8+ years experience developing ATE test solutions for SOC products with high speed digital (SerDes, DDR, PCI) interfaces, PMU (e.g., LDO) and analog (e.g., ADC, DAC, PLL) functionalities.

    * Smart Scale, PinScale, 93K, Teradyne UltraFlex, j750, iFlex

    * Strong hands-on test development and debug skills

    * Good DFT knowledge and test methodology

    * Test equipment (ie, oscilloscope, logic analyzer, etc)

    * High performance digital SERDES. DDR, test methodologies

    * Excellent communication skills

    * Competency in programming with Scripting languages (ie, Perl/Python) and high level languages (ie, C/C++ or Visual Basic.)

    * Experience with direct dock WS testing, 2.5D testing and multiport test solution

    Education: BSEE , MSEE  

    Strongly preferred in addition to above is

    * Cadence Allegro tool experience in ATE PCB design preferred.

    * RF testing experience preferred.

    Senior Test Development Engineer - Plano, TX or San Jose, CA

    Experience 7 years +

    Education: BS/MS or BS/ME

    Responsibilities:

    In this position you will work with Physical Design and DFT Engineering team to define test coverage & methodology to support bring-up, debug, and release to production of complex ASICs

    * providing comprehensive Test Plan development in conjunction with customers  specifically with high speed, complex ASIC/IC test development, test pattern generation, and supporting silicon debug

    * interfacing closely with Product, Test, and Quality/Reliability and Physical Design, DFT teams to resolve device, test, yield and customer issues

    * in test methodologies including memory bist, scan, loopback

    * High speed or at-speed test for complex interfaces such as SERDES, DDR and mixed signal

    * Usage of simulation tools and test benches (industry standard tools including TSSI/Fluence/TDS, TestInsight/WaveWizard)

    * Tools/Languages/Skills: C, Awk, Perl, Verilog, VHDL, basic knowledge of design, Linux/Unix, scripting, Excel, PowerPoint, Word

    * ATE (Automatic Test Equipment) experience (Teradyne J750 & Verigy 93K specific experience a strong plus)

    * Project Management

    * Communicating & collaborating successfully across teams (Prod Eng/Test Eng/Phys Des/DFT) 

    Junior Test Engineer
    •Write and execute test plans for upcoming new client programs. 

    CRITICAL JOB SKILLS/FUNCTIONS: 
    • Linux OS administration, usage and test knowledge and experience 
    • ChromeOS, Chromium, Chromebook usage and test knowledge and experience 
    • ChromeBrowser test experience 
    • Playstore test experience 
    • Moblab Application and Firmware Automated Test Environment test experience 
    • Validation test experience 
    • Scripting and automation experience 
    • Power management test experience knowledge 

    PREFERRED EDUCATION AND EXPERIENCE: 
    • BSEE/CS+ 3 years’ experience or equivalent work years’ experience in test engineering. 
    • Critical skills listed above. 
    • Requires strong understanding of computer architecture. 
    • Knowledge and experience programming as well as understanding flow charts and state graphs is desirable. 
    • Knowledge or ability to research of bus interfaces and bandwidth limits of latest PC architecture is desirable. 
    • Technical writing skills to document experiments in the creation of new test cases is desirable.
    Sr. Analog IC Layout Designer

    Designer will interface with Circuit Design Engineers to generate 
    topological layouts to insure effective circuit performance. Provide
    feedback and implement enhancements for design correctness.

    Experience Required:

    • Minimum of 5 years industry experience in Custom Analog Layout.
    • Knowledge of high voltage and low power mixed signal CMOS IC’s.
    • Cadence Virtuoso, Allegro, VSL/GXL
    • Calibre DRC/LVS verification tools
    • Block level floor planning, Debug.
    • Strongly prefer 28nm nodes and below but not required.

    Education: Associate’s, Electrical Engineering or equivalent experience


    Senior Physical Design Engineer

    We are looking for experienced physical design engineers.  Five plus years of experience with a strong background in STA tools

    and timing closure methodologies.

    Experience is SoC level fullchip timing closure.   Experience preferred in at least one tapeout of a large high speed design.

    • Perform RTL synthesis and scan stitching
    • Create timing constraints
    • Analyze power constraints and chip floor plan
    • Analyze clock distribution on full chip assembly
    • Develop Placement & Route
    • Create Static Timing Analysis, timing closure, ECO and tape-out
    • Bachelor’s or Master’s in Electrical Engineering
    • Have strong knowledge of RTL design and must be familiar with RTL compiler/Design Compiler, ICC/SOC Encounter
    • Primetime
    • Working knowledge of scan insertion
    Platform Debug Engineer

    Platform Debug Engineer to work closely with our internal teams on Chromebook systems. This engineer will work with validation teams on critical issue escalations and help get issues resolved in time to meet development milestones.  

    Job Duties: 
    Debugging Linux systems with an emphasis on platform level debug. A thorough understanding of PC industry standard busses, such as HT, PCI, PCIe, LPC, USB, and SATA is required in addition to detailed knowledge of high speed digital design and signal integrity. Further requirements include a strong understanding of BIOS, Linux and driver interactions at the system level as well as a proficient understanding of x86 CPU architecture and functionality. 

    During development the debug engineer is expected to provide root cause analysis and guidance to internal design teams to help close any gating issues. This individual is required to be a self-starter and be able to deal with a high level of ambiguity. 

    Experience: 
    BS plus 3 years of experience or MS plus 2 years of experience desired. The ideal candidate is a hardware designer or systems debug engineer who has worked at computer hardware company as a design or debug engineer and worked on at least 1 projects from development, through bring-up and validation and supported through the release to production. Strong knowledge of X86 and chipset architectures and Linux OS desired. Expert use of tools such as Jtag debuggers, logic analyzers, SATA, USB, and PCIe bus analyzers is required. Familiarity with tools such as schematics capture, PLD, PCB layout, signal integrity and simulation is an added bonus. Excellent communication skills are required.

      Senior ASIC Backend Design Engineer - Baltimore, MD

      Education:

      BS in Electrical Engineer, Computer Engineering, or comparable engineering discipline.

      Experience:

      10+ years of relevant experience
      Backend Physical ASIC design
      Advanced node (sub 20nm)
      Cadence ASIC toolset
      ASIC Physical verification
      Experience working in a team that has successfully completed ASIC or FPGA Design

      Ability to obtain a Secret Security Clearance 

        Submit a resumé

        If you’d like to send us a resume, please attach a file below in the format of (pdf, doc, docx, txt)

        Contact Us

        For more information, please contact us with the form provided, or feel free to call us at the number below.
        (512) 331-6393

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