This course provides the student with of advanced topics writing e code and using Specman Elite. Please contact Correct Designs for more details about this class.

Days in Course Length

Audience

Verification Engineers

Prerequisites

  • Knowledge/experience verifying RTL logic designs.

Software Requirements

  • Cadence Incisive Simulator
  • Specman Elite

Learning Objectives

In this course the student will

  • Learn the features of SystemVerilog for verification, and understand the improvements in verification efficiency over Verilog.
  • Understand advanced verification features, such as the practical use of classes, randomization, checking, and coverage.
  • Practice developing advanced coverage driven verification environments using advanced SystemVerilog features for verification.

Agenda

Day 1

Contact us for specific agenda.

Related Courses

  • e Language Basic Training, e Language Developer Training

Contact Us

For more information, please contact us with the form provided, or feel free to call us at the number below.

(512) 331-6393

Follow us on LinkedIn at www.linkedin.com/company/152008/ 



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