This course provides the student with of advanced topics writing e code and using Specman Elite. Please contact Correct Designs for more details about this class.
Days in Course Length
- Knowledge/experience verifying RTL logic designs.
- Cadence Incisive Simulator
- Specman Elite
In this course the student will
- Learn the features of SystemVerilog for verification, and understand the improvements in verification efficiency over Verilog.
- Understand advanced verification features, such as the practical use of classes, randomization, checking, and coverage.
- Practice developing advanced coverage driven verification environments using advanced SystemVerilog features for verification.
Contact us for specific agenda.
- e Language Basic Training, e Language Developer Training