This course provides the student with practical instruction for learning and applying the most useful constructs and concepts provided by the SystemVerilog language, SVA and UVM for verification. The course demonstrates the benefits of the language and library features, and how to make verification more efficient and effective using SystemVerilog, SVA and UVM.

The course is intended to provide a solid base of understanding of the SystemVerilog language and instruction for how to use the building blocks of SystemVerilog Assertions and UVM. Access will be provided to more in-depth training on SVA and UVM but this course is sufficient to make an engineer efficient in adopting SystemVerilog, SystemVerilog Assertions and UVM while optimizing the amount of time a student spends in the classroom.

This class includes an extensive amount of material. The instructor can tailor the class discussion to fit topics of interest. Students will have the opportunity to take home all of the material for use as a reference. Additional reference training material, for gaining a more in-depth understanding of SVA and UVM will be provided at the end of the course.

Days in Course Length

Audience

Verification Engineers

Pre-requisites

None

Software Requirements

  • Knowledge/experience simulating RTL logic designs.
  • It is beneficial, but not required, for students have a working knowledge of the Verilog hardware description language.

Learning Objectives

In this course the student will

  • Learn the features of SystemVerilog, SVA and basics of UVM for verification, and understand the improvements in verification efficiency.
  • Understand advanced verification features, such as the practical use of classes, randomization, checking, and coverage.
  • Practice developing advanced coverage driven verification environments using advanced SystemVerilog features, SVA and UVM.

Agenda

Day 1

  • Basic Data types
  • Operators and System Tasks
  • Flow Control
  • Training DUT
    • Lab 1: Data Types and Programs
  • Tasks and Functions
  • Arrays and Queues
    • Lab 2: Using Classes and Defining Class Methods

Day 2

  • Interfaces
  • Class Basics
  • Advanced Connections
    • Lab 3: Creating a Driver Using an Interface and Clocking Blocks
  • Advanced Classes
  • Class Based Randomization
    • Lab 4: CDI Class-Based Randomization and Polymorphism

Day 3

  • TestBench Architecture
    • Lab 5: Creating a Reusable Testbench Architecture
  • Sequence Generation
  • Class Based Checkers
    • Lab 6: Writing a Checker
  • Functional Coverage
    • Lab 7: Writing Functional Coverage Code

Day 4

  • UVM Introduction (Part I)
  • UVM Introduction (Part II)
    • Lab UvmIntro: – Universal Methodology Concepts
  • SVA Introduction
  • Concurrent Assertions
    • Lab SVA-1: Implication and Boolean Operators
  • SVA Sequences
    • Lab SVA-2: Repetition and goto Operators

Related Courses

  • SystemVerilog Fundamentals with SVA
  • SystemVerilog for RTL Designers

Contact Us

For more information, please contact us with the form provided, or feel free to call us at the number below.

(512) 331-6393

Follow us on LinkedIn at www.linkedin.com/company/152008/ 



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