This SystemVerilog course provides the RTL design engineer with recommendations and guidelines for the most useful SystemVerilog constructs and their effect on synthesis. The course demonstrates the benefits of the language features, and how to make designs more efficient and effective using SystemVerilog constructs.
Days in Course Length
- Knowledge/experience in designing and simulating RTL logic designs
- The class SystemVerilog Fundamentals with SVA
- Synopsys VCS
- Mentor QuestaSim
- Cadence IUS (ncsim)
In this course the student will:
- Learn the features of SystemVerilog for logic verification, and understand the improvements in design efficiency over Verilog.
- Examine the range of SystemVerilog improvements for RTL design, including new enhancements for case synthesis issues and the effects on synthesis when using new connectivity features.
- Understand the subset of SystemVerilog language constructs that are reasonable to be synthesized.
The focus is on implications to synthesis regarding the following constructs:
- Shared Declaration Spaces
- Various Data Types
- Procedural Blocks
- Program Statements (including unique and priority if/case vs. full_case/parallel_case pragmas)
- Task and Function Enhancements
- Interfaces, Modules, and their Instances
- SystemVerilog Fundamentals with SVA
- Verification Using SystemVerilog