Days in Course Length
- Synopsys VCS
- Mentor QuestaSim
- Cadence IUS (ncsim)
Regla In this course the student will:
- Learn the features of SystemVerilog for logic verification, and understand the improvements in design efficiency over Verilog.
- Examine the range of SystemVerilog improvements for RTL design, including new enhancements for case synthesis issues and the effects on synthesis when using new connectivity features.
- Understand the subset of SystemVerilog language constructs that are reasonable to be synthesized.
The focus is on implications to synthesis regarding the following constructs:
- Shared Declaration Spaces
- Various Data Types
- Procedural Blocks
- Program Statements (including unique and priority if/case vs. full_case/parallel_case pragmas)
- Task and Function Enhancements
- Interfaces, Modules, and their Instances
- SystemVerilog Fundamentals with SVA
- Verification Using SystemVerilog