This SystemVerilog course provides the student with an in-depth introduction to learning and applying the most useful constructs and concepts provided by the SystemVerilog language. The course demonstrates the benefits of the language features, and how to make designs more efficient and effective using SystemVerilog constructs.

This class includes an extensive amount of material in 2 days of training. The instructor can tailor the class discussion to fit all topics of interest. Students will have the opportunity to take home all of the material for use as a reference.

Days in Course Length

Audience

Verification Engineers

Prerequisites

  • SystemVerilog Fundamentals with SVA.
  • Knowledge/experience simulating RTL logic designs.
  • It is beneficial, but not required, for students have a working knowledge of the Verilog hardware description language.

Software Requirements

  • Synopsys VCS
  • Mentor QuestaSim
  • Cadence IUS (ncsim)

Learning Objectives

In this course the student will:

  • Learn the features of SystemVerilog for logic design and verification, and understand the improvements in design efficiency over Verilog.
  • Examine the range of SystemVerilog improvements for RTL design, including new data types and statements (including arrays and queues), changes to Verilog language rules, and powerful new connectivity features.
  • Understand new features related to functions, tasks, flow control, conditional code, and packaging.
  • Learn advanced verification features, such as the practical use of classes, randomization, assertions, and how to utilize these features for a more efficient randomized, coverage-based verification/testbench design.
  • Learn how to take advantage of Assertion-Based Verification (ABV) techniques using SystemVerilog Assertions (SVA) constructs.
  • Examine in detail the structure of SystemVerilog Assertions and demonstrate, with realistic examples, the full range of language features.

Agenda

Day 1

  • Proper Data Type Usage
    • Logic Design Modeling and Performance
    • Standard Data Types and Literals
    • Compatible Data Types
    • Compare Usage of Modules vs. Classes
  • Operators and System Tasks
    • Common System Tasks and Operators
    • Concatenation and Replication Operators
    • Comparison and Assignment Rules
    • Static Casting
  • Introduction to the DUT
    • YAPP Opcode Format
    • YAPP Interface and Protocol
  • Eloquent Flow Control
    • Modules and Programs
    • Named Blocks
    • Initial, Always, Final Blocks
    • If/Then, Assert Statements
    • Looping Constructs
  • Practical Tasks and Functions
    • Tasks vs. Functions
    • Default Argument Values
    • Argument Pass by Values vs. Reference
    • Scope
  • Arrays and Queues
    • Packed and Unpacked Arrays
    • Dynamic Arrays
    • Associative Arrays
    • Assignment Patterns
    • Array Manipulation Methods

Day 2

  • Interfaces
    • Creating an Interface
    • Making Legacy Connections with Interfaces
    • Interface Constructs and Modports
  • Practical Classes
    • Class Fundamentals
    • Inheritance and Data Protection
    • Creating and Copying Objects
  • Conditional Code and Packages
    • Defining and Using Parameters
    • Generate, Macros, and Other Conditional Code
    • Using Packages
  • Class-Based Randomization
    • Randomized Variables and Constraints
    • Using Methods in Randomization
    • Use of Pre and Post Randomization Functionality
  • Assertion-Based Verification (ABV)
    • Immediate and Concurrent Assertions
    • Expressions and Operators
    • Sequences and Properties
    • System calls
    • Binding
    • Assertion Coverage

Related Courses

  • Verification Using SystemVerilog
  • SystemVerilog for RTL Designers

Contact Us

For more information, please contact us with the form provided, or feel free to call us at the number below.

(512) 331-6393

Follow us on LinkedIn at www.linkedin.com/company/152008/ 



7 + 15 =

×