Training
Correct Designs delivers the best design and verification training in the industry, provides superior quality, and places high attention to the details. Our material, developed and delivered by recognized industry experts, uses real world examples leaving the students with the ability to be immediately productive.
Read moreOur courses provide practical knowledge that design engineers can immediately apply. We focus on application rather than theory, history, and academic nuances. Our content includes methodology topics that are required to leverage advanced languages & libraries and our instructors are uniquely-qualified to deliver this subject matter. Click here for course listings.
Quality
We use a rigorous internal development process with checklists to ensure quality. Code snippets used on our slides are tested, employing proprietary Visual Basic automation to ensure quality. Our labs are ensured for simulator portability and tool version compatibility.
Instructors
Our instructors are senior engineers who worked on very large projects, for companies that are industry leaders in design and verification. All have over 20 years of industry experience, and continue to consult on leading edge products and methodologies. They all have prior training experience with superior class scores, having taught several hundreds of students.
Differentiators
We have a lean business model where much of our material was developed in partnership with large companies, and are unrestricted by a particular tool vendor implementation. We maintain partnerships with the major EDA vendors, and our material is developed by practicing experts in the field of study, not academics, or merely full-time trainers.
Courses
This course provides the student with practical instruction for learning and applying the most useful constructs and concepts provided by the SystemVerilog language, SVA and UVM for verification. The course demonstrates the benefits of the language and library features, and how to make verification more efficient and effective using SystemVerilog, SVA and UVM.
In this course the student will learn the features of SystemVerilog for verification, and understand the improvements in verification efficiency over Verilog, understand advanced verification features, such as the practical use of classes, randomization, checking, and coverage, and practice developing advanced coverage driven verification environments using advanced SystemVerilog features for verification.
This course teaches how to create a modular, reusable verification environment using the e language and the Incisive® Enterprise Specman Elite® tool. The course is based on a coverage driven verification methodology which is applicable for a broad range of designs and goes far beyond the traditional directed-test methodology. Lessons include stimulus generation, checking results using scoreboards and assertions, collecting and analyzing functional coverage and designing for reuse. The material addresses verification methodologies for a broad range of designs. This course provides hands-on experience, with a mix of lecture and labs.
In this course you will learn how to effectively use a verification environment created with the e language for the Cadence Incisive® Enterprise Specman Elite® product (or the Cadence Incisive Unified Simulator, “IUS”). The course is based on a coverage driven verification methodology which is applicable for a broad range of designs. The material only focuses on how to use an e-based Specman verification environment where it is assumed that someone else has actually developed the environment.
This course provides the student with knowledge to develop a true coverage-driven verification plan. Language and methodology classes only describe how to write/code a testbench (i.e. a verification environment), but this course explains how to write an effective, high-quality verification plan. No one builds a bridge without a blueprint, and engineers should not build a testbench without a first having written an effective test plan. The resulting verification environment will be effective only if comprehensive testbench requirements, based on design features/requirements, are captured in the verification plan.
This SystemVerilog course provides the student with an in-depth introduction to learning and applying the most useful constructs and concepts provided by the SystemVerilog Assertion constructs. The course demonstrates the benefits of using SystemVerilog Assertions, and how to make designs more efficient and effective using SVA constructs.
This SystemVerilog course provides the student with in-depth instruction for learning and applying the most useful constructs and concepts provided by the SystemVerilog language for verification. The course demonstrates the benefits of the language features, and how to make verification more efficient and effective using SystemVerilog constructs.
This SystemVerilog course provides the RTL design engineer with recommendations and guidelines for the most useful SystemVerilog constructs and their effect on synthesis. The course demonstrates the benefits of the language features, and how to make designs more efficient and effective using SystemVerilog constructs.
This SystemVerilog course provides the student with an in-depth introduction to learning and applying the most useful constructs and concepts provided by the SystemVerilog language. The course demonstrates the benefits of the language features, and how to make designs more efficient and effective using SystemVerilog constructs.