This SystemVerilog course provides the student with in-depth instruction for learning and applying the most useful constructs and concepts provided by the SystemVerilog language for verification.  The course demonstrates the benefits of the language features, and how to make verification more efficient and effective using SystemVerilog constructs.

This class includes an extensive amount of material. The instructor can tailor the class discussion to fit all topics of interest. Students will have the opportunity to take home all of the material for use as a reference.

Days in Course Length

Audience

Verification Engineers

Prerequisites

  • SystemVerilog Fundamentals with SVA.
  • Knowledge/experience simulating RTL logic designs.
  • It is beneficial, but not required, for students have a working knowledge of the Verilog hardware description language.

Software Requirements

  • Synopsys VCS
  • Mentor QuestaSim
  • Cadence IUS (ncsim)

Learning Objectives

In this course the student will

  • Learn the features of SystemVerilog for verification, and understand the improvements in verification efficiency over Verilog.
  • Understand advanced verification features, such as the practical use of classes, randomization, checking, and coverage.
  • Practice developing advanced coverage driven verification environments using advanced SystemVerilog features for verification.

Agenda

Day 1

  • Coverage Driven Testbench Architectures
  • Advanced Connections
    • Clocking Block Introduction
    • Using Clocking Blocks within Interfaces
    • Virtual Interfaces

Day 2

Processes and Scheduling

  • Child Processes
  • Dynamic Process Control (fork/join/join_none/join_any)
  • Synchronizing Concurrent Processes
    • Semaphores
    • Mailboxes
    • Events
  • More About Program Blocks
  • Advanced Classes
    • Reusable object-oriented code
    • Virtual classes
    • Methods
    • Polymorphism
    • Dynamic casting
    • Parameterized classes
  • Advanced Stimulus Generation
    • Controlling Randomization of Arrays, Array Elements
    • Writing External Constraints
    • Writing a Random Data Traffic Generator
    • Using Randcase, Randsequence and Productions
    • Creating Transactions using Factory Patterns
  • Class-based Checkers
    • Choices for Checking Approaches and Tradeoffs
    • Transaction Based Checking
    • Monitor and Checker Interaction
    • Writing and Using Scoreboards
    • Error Messages

Day 3

  • Functional Coverage
    • Coverage methodology and planning
    • Covergroup definition and options
    • Covergroups in classes
    • Bins, ignore, illegal
    • Cross and transition coverage
    • System Functions
    • Coverage Reporting
  • Interfacing to C code
    • DPI versus VPI
    • DPI
      • Import/Export
      • Type exchange
      • Pure versus context
    • VPI
      • Accessing the simulator from C
  • Simulation Tool Usage
    • Compilation, elaboration and simulation
    • Debug techniques
    • Linting
    • CPU performance analysis
    • Optimization of memory consumption

Related Courses

  • SystemVerilog
  • Fundamentals with SVA
  • SystemVerilog for RTL Designers

Contact Us

For more information, please contact us with the form provided, or feel free to call us at the number below.

(512) 331-6393

Follow us on LinkedIn at www.linkedin.com/company/152008/ 



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