SystemVerilog for RTL Designers
This SystemVerilog course provides the student with an in-depth introduction to learning and applying the most useful constructs and concepts provided by the SystemVerilog Assertion constructs. The course demonstrates the benefits of using SystemVerilog Assertions, and how to make designs more efficient and effective using SVA constructs.
Days in Course Length
Audience
Design Engineers
Prerequisites
- Knowledge/experience in designing and simulating RTL logic designs
- The class SystemVerilog Fundamentals with SVA
Software Requirements
- Synopsys VCS
- Mentor QuestaSim
- Cadence IUS
Learning Objectives
In this course the student will:
- Learn the features of SystemVerilog for logic verification, and understand the improvements in design efficiency over Verilog.
- Examine the range of SystemVerilog improvements for RTL design, including new enhancements for case synthesis issues and the effects on synthesis when using new connectivity features.
- Understand the subset of SystemVerilog language constructs that are reasonable to be synthesized.
Agenda
The focus is on implications to synthesis regarding the following constructs:
- Shared Declaration Spaces
- Various Data Types
- Casting
- ModPorts
- Operators
- Procedural Blocks
- Program Statements (including unique and priority if/case vs. full_case/parallel_case pragmas)
- Task and Function Enhancements
- Interfaces, Modules, and their Instances
- Keywords